1. Field
Advancements in integrated circuit design for testability are needed to provide improvements in performance, efficiency, and utility of use.
2. Related Art
Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes. Nothing herein is to be construed as an admission that any of the references are pertinent prior art, nor does it constitute any admission as to the contents or date of actual publication of these documents.
Integrated circuit chips must be tested for manufacturing flaws. Manufacturing flaws are often modeled using fault models. The Stuck-At fault model is the most basic fault model. A Stuck-At fault occurs when a particular connection in the circuit remains at (“stuck at”) a low level (known as Stuck-At 0 or SA0) or remains at (“stuck at”) a high level (known as Stuck-At 1 or SA1). A SA0 fault on a connection is detected when the circuit is controlled to place a 1 (high) value on that connection, but a 0 (low) value is observed on that connection. A SA1 fault on a connection is detected when the circuit is controlled to place a 0 value on that connection, but a 1 value is observed on that connection. Circuits whose internal connections are easily controlled and observed are more testable than circuits whose internal connections are more difficult to control and observe.
Scan testing is a widely used technique to detect manufacturing defects in integrated circuits. In a scanned circuit, some or all of the flip-flops are replaced by scan flip-flops. A scanned circuit is using “full scan” if all the flip-flops are scan flip-flops; otherwise the circuit is using “partial scan”. Scan provides a method of increasing the controllability and observability of a circuit.
Mux-scan is the most common method of implementing scan test. A mux-scan flip-flop has two modes: a normal operation mode and a scan shift mode. During normal operation mode, the scan flip-flops implement the user's desired (non-test mode) behavior. During scan shift mode, the scan flip-flops are interconnected into one or more shift registers (scan chains).
FIG. 1 shows a prior-art mux-scan flip-flop with asynchronous reset and asynchronous preset pins. When the SE (scan enable) pin is at a 0 value, the flip-flop is in normal operation mode. When the SE pin is at a 1 value, the flip-flop is in scan shift mode. In both normal operation mode and scan shift mode, the CLK pin is used to clock data into the flip-flop. A 0 value on the RN asynchronous pin loads the flip-flop with a 0 value. A 0 value on the SN asynchronous pin loads the flip-flop with a 1 value. The SN asynchronous preset and RN asynchronous reset pins both must remain at a 1 value during scan shift mode. Otherwise, incorrect values will be loaded into the scan chains.
Flip-flops may be designed to have reset priority (i.e., when SN and RN both have a 0 value, the flip-flop is asynchronously loaded with a 0 value). Flip-flops may also be designed to have preset priority (i.e., when SN and RN both have a 0 value, the flip-flop is asynchronously loaded with a 1 value).
By placing the scan flip-flops in scan shift mode and applying clocks, values can be loaded into the scan flip-flops (scan-in operation) and extracted from the scan flip-flops (scan-out operation). A typical scan test sequence is: scan-in, normal operation (with one or more clocks applied to the circuit), and scan-out. Circuit defects are detected when the scan-out values do not match the expected values for a good circuit. One scan test sequence can detect multiple faults.
To test a circuit, multiple scan test sequences are usually needed. Automated Test Pattern Generation (ATPG) programs usually generate the scan test sequences. The ATPG programs use the scan flip-flops as control points (values can be scanned in) and observe points (values can be scanned out) when creating scan test sequences to detect faults. In general, given two circuits that perform the same “normal operation” behavior—with one circuit using full scan and the other circuit using partial scan—ATPG programs work more effectively with the circuit that uses full scan and can generate scan test sequences capable of detecting a higher percentage of manufacturing defects.
In order to use scan testing, the circuit must obey many “design-for-test rules (DFT rules). Obeying DFT rules increases the cost and time of developing circuits. DFT rule violations must be corrected, and the designer must also verify that fixing the DFT rule violations did not introduce errors in the circuit's normal operation. Designers may choose to not fix some DFT rule violations, and therefore must replace the violating scan flip-flops with non-scan flip-flops, resulting in a partial scan design.
Designers often prototype in FPGAs, and when higher performance and/or lower cost is desired, the FPGA-based designs are converted to a gate array, logic array, or standard cell implementation. Since the FPGA devices are pre-tested, the designer usually does not consider scan and its associated DFT rules when developing the design. However, the designer is responsible for ensuring that the gate array, logic array, or standard cell implementation is tested, and usually uses scan test. At this point, obeying DFT rules can cause major changes in the design. A test methodology that is transparent to the designer while still providing the testability associated with “full scan” testability would be a major advantage for getting to market quicker.
Existing technologies such as gate arrays and new technologies such as logic arrays allow user-designed circuits to be manufactured quicker than if the user-designed circuit was implemented in standard cell. Gate arrays and logic arrays both use pre-designed logic that can be configured by routing to implement a user-design circuit. Manufacturing steps prior to customization routing can be done before the user-designed circuit has been designed.
The pre-designed logic in a gate array has usually been implemented using custom designed logic. Custom designed logic usually requires more time to design and to validate than logic implemented in standard cell.
The Modular Array, also known as structured array and more recently as a logic array, uses standard cells to implement the pre-designed logic. This technique is described in U.S. patent application Ser. No. 10/447,465, filed May 28, 2003, and published Dec. 2, 2004 as Publication No. US 2004/0243966, Modular Array Defined by Standard Cell Logic, which is owned by the owner of the instant application, and to the extent permitted by the type of the instant application, is herein incorporated by reference for all purposes. Constructing logic array building blocks from standard cells allow logic arrays to be implemented more quickly than if custom designed logic was used to implement the building blocks.
The available macros of both gate-arrays and logic arrays are implemented as a base array portion of pre-designed lower layers and a customization portion of at least one upper layer. These macros are necessarily pre-selected and pre-placed. (This is in contrast with conventional standard cell design, which permits the designer of the application circuit to make largely unrestricted selection and placement of instances of cells copied from a standard cell library.) The available macros are allocated to the corresponding functions of the application (user) circuit netlist. For gate-arrays, the macros are implemented using custom circuit design and generally are relatively primitive functions. For logic arrays, the macros are implemented using a pre-existing standard cell library (that frequently is specified by the user rather than the logic array tool vendor) and generally include both primitive and relatively higher-order functions.
Since standard cells are used to implement the logic array's pre-designed logic, mux-scan can certainly be used to test user-designed circuits. However, the designer must follow all the associated DFT rules. Providing a test method that insures effortless automatic compliance with DFT rules and is compatible with logic arrays, would make it even easier and faster for a designer to have a user-designed circuit manufactured.
Partition test is a concept described in U.S. Pat. Nos. 6,223,313 and 6,611,932, which are owned by the owner of the instant application, and to the extent permitted by the type of the instant application, are herein incorporated by reference for all purposes.